Exemplary embodiments relate to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device having a three dimensional (3-D) structure and a method of manufacturing the same.
When a flash memory device is operated, if a lot of current flows from a plurality of bit lines to source contact plugs coupled to a common source line, a source line bouncing phenomenon in which a voltage of the common source line is shifted by resistance of the source contact plugs occurs. The source line bouncing phenomenon deteriorates the characteristic of the flash memory device. The deterioration of the characteristic of the flash memory device due to the source line bouncing phenomenon is described in detail below.
The memory cell array of a flash memory device includes a plurality of memory strings. Each of the memory strings includes memory cells coupled in series. Furthermore, the drain of the memory string is coupled to a bit line. The plurality of memory strings coupled to the respective bit lines is in common coupled to a common source line through the source contact plugs. Furthermore, the gate of each of the memory cells forming the memory string is coupled to a word line.
In order to write data in a selected memory cell, a program operation and a verify operation are repeatedly performed within the set number of times until the selected memory cell is programmed. In the verify operation, the voltage of a bit line coupled to the selected memory cell is precharged to a high level. Next, whether the selected memory cell has been programmed is determined according to whether the voltage of the bit line has been changed by supplying a verify voltage to a word line coupled to the selected memory cell. That is, when the threshold voltage of the selected memory cell is the verify voltage or higher (that is, the selected memory cell has been programmed), the voltage of the bit line maintains a high level. If the threshold voltage of the selected memory cell has not reached the verify voltage (that is, the selected memory cell has not been programmed), the bit line is coupled to the common source line and thus the voltage of the bit line is discharged from a precharge level to a ground voltage. At this time, if the voltage of the common source line rises due to resistance of the source contact plugs coupling the common source line and the memory string coupled to the bit line, the source voltage of the selected memory cell also rises. The voltage of the common source line may be shifted depending on the program states of unselected memory cells coupled to the word line.
For example, if a verify operation is performed on the selected memory cell in the state in which all the unselected memory cells coupled to the word line have not been programmed, the voltage of the common source line may rise. Consequently, the selected memory cell may be verified to have been programmed because the voltage of the bit line is not discharged from the precharge level although the selected memory cell has not been programmed. All the unselected memory cells coupled to the word line may be programmed through a subsequent program operation. In this case, if a read operation is performed on the selected memory cell, the threshold voltage of the selected memory cell may be read as being lower than that in the verify operation because noise due to the common source line is reduced as compared with noise when the unselected memory cells are not programmed.
There occurs an under-programmed cell that is determined to have been programmed although the cell has not been programmed due to the source line bouncing phenomenon in which the voltage of the common source line is shifted according to the program states of peripheral cells as described above. The under-programmed cell increases the width of a distribution of the threshold voltages of memory cells for a specific program state. The source line bouncing phenomenon that deteriorates the characteristic of the flash memory device as described above becomes worse according to an increase in the resistance of the source contact plugs coupled to the common source line.
In a 3-D structured semiconductor memory device in which memory cells are stacked in a direction vertical to a semiconductor substrate in order to increase the degree of integration of the memory cells, a plurality of cell strings is commonly coupled to the source contact plugs with high resistance in terms of a structural characteristic. For this reason, the source line bouncing phenomenon becomes worse in the 3-D structured semiconductor memory device. Accordingly, a method of improving the source line bouncing phenomenon is useful.